module i2c_test_top;
    import uvm_pkg::*;
    `include "test_collection.sv"
    parameter simulation_cycle = 100 ;
    bit  clk;
    bit  rst=1;

    ic2_if vif(clk);
    i2cSlaveTop dut(
        .clk(vif.clk),
        .rst(vif.rst),
        .sda(vif.sda),
        .scl(vif.scl),
        .myReg0(vif.myReg0)
    );


    initial begin
        vif.rst = 1;
        @(posedge clk);
        @(posedge clk);
        @(posedge clk);
        @(posedge clk);
        @(posedge clk);
        @(posedge clk);
        vif.rst = 0;
        @(posedge clk);
        @(posedge clk);
        @(posedge clk);
    end

    initial begin
        $fsdbDumpfile("dump.fsdb");
        $fsdbDumpvars(0,i2c_test_top);
        $fsdbDumpSVA;
        forever #(simulation_cycle/2) clk = ~clk ;
    end

    initial begin
        uvm_reg::include_coverage("*", UVM_CVR_ALL);
        $timeformat(-9, 1, "ns", 10);

        //Step6: add run_test to create the uvm_test
        run_test();
    end

endmodule
